
module FIR_Loader
#(
    parameter STAGE=8,
    parameter WIDTH=8
)
(
    input wire i_clk,
    input wire i_rst,
    input wire i_config,
    output wire o_cclk,
    output wire signed [WIDTH-1:0]o_Coeff,
    output wire o_config_done
);
reg signed [7:0] coef0;
reg signed [7:0] coef1;
reg signed [7:0] coef2;
reg signed [7:0] coef3;
reg signed [7:0] coef4;
reg signed [7:0] coef5;
reg signed [7:0] coef6;
reg signed [7:0] coef7;

reg state;

        coef0<=-27;
        coef1<=16;
        coef2<=74;
        coef3<=117;
        coef4<=117;
        coef5<=74;
        coef6<=16;
        coef7<=-27;

always @(posedge i_clk or posedge i_rst) begin
    if(i_rst) begin
        state<='b0;
    end
    else begin
        
    end
end